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| S5C7320X01 DATA SHEET PRODUCT SUMMARY 100-TQFP-1414 INTRODUCTION S5C7320X01 receives digital data from CCD-using video camera systems such as MMPC and surveillance cameras, and outputs combined video signals. It also runs algorithms for AE/AWB and transmits them to MICOM, or carries out AE/AWB independently. S5C7320X01 has the following features; FEATURES * * * * * * * NTSC/PAL, 360H/510H/720H/760H CCD compatible Able to detect and correct 64 CCD white defects Built-in digital clamp feature 3-line processing using 2 line memories Luminance signal process Chrominance signal process Color difference signal modulation using quadrature subcarrier generation (DTO) method Built-in timing and sync signal generator External synchronization compatible (Line-lock, H-reset/V-reset, H-PLL/V-reset) Built-in ability to determine if in external synchronization mode Serial MICOM interface Built-in algorithm for AE/AWB MICOMless (stand-alone) full AE/AWB Partial linear approximation method's compensation feature for R, G, B and luminance Built-in 2CH DAC for combined Y/C analog output EEPROM interface for register setting without MICOM Built-in EVR interface for controlling CDS/AGC, and CCD Device S5C7320X01-T0R0 Package 100-TQFP-1414 Operating Tempertature 0 C - 70 C ORDERING INFORMATION * * * * * * * * * * APPLICATIONS * * * Camcorder Surveillance camera Multimedia PC (MMPC) camera 1 DATA SHEET S5C7320X01 PIN CONFIGURATION C C D 8 C TT V V CS SSXY Y YYSY YYYDCCCC DC T T COOOOS OOOODOOOO 9E10K76544321037654 V SCCCC S OOOO 33210 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 VDD5 SECK SECSN SED ADCK V4 SG2 V3 VSS5 SG1 V1 V2 SUB VSS6 H1 H2 VDD6 S5C7520X01 WB1 WB0 WBRNG SS2 SS1 SS0 FSHTR VDDA2 VSSA2 AC VREF IREF VBB COMP AY VSSA1 VDDA1 EHD EVD RSTN SMO SMI SMCK SMCSN BLC VPXXRSSVCC S C1 2 GHHDL L S1 P DDP P 1 113 24 PVHFV B DDL S L DS K 2 L S F E CPHC SA IC YLGI N HR C V D D 2 S R D A O S R D A I S R C K M I C O M Figure 1. Pin Configuration 2 S5C7320X01 DATA SHEET PIN DESCRIPTION Table 1. Pin Description No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name VSS1 PC1 X1 X2 RG SHP SHD VDD1 CLP12 CLP34 PBLK VD HD FLD VSS2 LSFE CSYNC PAL HIGH CCIR VDD2 SRDAO SRDAI SRCK MICOM BLC SMCSN SMCK SMI SMO RSTN EVD I/O G O I O O O O P O O O O O O G O O I I I P O I O I I I I I O I I Ground Phase comparator output for main clock PLL Main X-TAL input Main X-TAL output Reset gate pulse Precharge sample & hold pulse Data sample & hold pulse Power Clamp pulse 12 (CLP1/CLP2 multiplexing) Clamp pulse 34 (CLP3/CLP4 multiplexing) Pre-blank pulse Vertical drive pulse Horizontal drive pulse Field ID signal Ground Low shutter enable signal (or Vsynco) Composite sync (or Hsynco) PAL mode (L: NTSC, H: PAL) High mode (L: Normal, H:HI8) CCIR format mode (L: CIF, H: CCIR) Power EEPROM data output EEPROM data input EEPROM control clock Stand-alone/MICOM IF selection (L: stand-alone) Back light compensation enable Serial MICOM chip select enable (active "L") Serial MICOM input clock Serial MICOM data input Serial MICOM data output Master reset (active low) EXT. sync. VD input (line-lock/V-reset mode) P-up P-down P-down Schmitt Schmitt Schmitt P-down P-down P-down Description Note 3 DATA SHEET S5C7320X01 Table 1. Pin Description (Continued) No 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name EHD VDDA1 VSSA1 AY COMP VBB IREF VREF AC VSSA2 VDDA2 FSHTR SS0 SS1 SS2 WBRNG WB0 WB1 CO0 CO1 CO2 CO3 VSS3 CO4 CO5 CO6 CO7 VDD3 YO0 YO1 YO2 YO3 I/O I P G O(A) I(A) G I(A) I(A) O(A) G P I I I I I I I O O O O G O O O O P O O O O Description EXT. sync. HD input (separate sync., composite sync. locking mode.) Analog power for DAC Analog ground for DAC Analog luminance output Compensation terminal for DAC DAC bulk bias (ground) Current reference terminal Voltage reference terminal Analog CHROMA output Analog ground for DAC Analog power for DAC Fixed high speed shutter mode (active H) Fixed high speed shutter control 0 Fixed high speed shutter control 1 Fixed high speed shutter control 2 White balance range selection White balance mode 0 White balance mode 1 Digital CHROMA output (LSB) Digital CHROMA output Digital CHROMA output Digital CHROMA output Ground Digital CHROMA output Digital CHROMA output Digital CHROMA output Digital CHROMA output (MSB) Power Digital luminance output (LSB) Digital luminance output Digital luminance output Digital luminance output P-down P-down P-down P-down P-down P-down Pull-up Note P-up 4 S5C7320X01 DATA SHEET Table 1. Pin Description (Continued) No 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Name VSS4 YO4 YO5 YO6 YO7 XCK TST0 TST1 SCE CCD9 CCD8 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 VDD5 SECK SECSN SED ADCK V4 SG2 V3 VSS5 SG1 V1 V2 SUB VSS6 I/O G O O O O I I I I I I I I I I I I I I P O O O O O O O G O O O O G Ground Digital luminance output Digital luminance output Digital luminance output Digital luminance output (MSB) Encoder external clock input for line-lock Test pin 0 (active high) Test pin 1(active high) Scan enable for test (active high) CCD data input [MSB] CCD data input CCD data input CCD data input CCD data input CCD data input CCD data input CCD data input CCD data input CCD data input [LSB] Power CDS/AGC, EVR clock CDS/AGC, EVR chip select (acitve low) CDS/AGC, EVR data line ADC sampling clock Vertical drive pulse 4 for CCD CCD sensor read out pulse 2 Vertical drive pulse 3 for CCD Ground CCD sensor read out pulse 1 Vertical drive pulse 1 for CCD Vertical drive pulse 2 for CCD CCD discharge pulse Ground for H1, H2 "L" "L" "L" "L" Description Note 5 DATA SHEET S5C7320X01 Table 1. Pin Description (Continued) No 98 99 100 Name H1 H2 VDD6 I/O O O P Description Horizontal driving pulse 1 for CCD Horizontal driving pulse 2 for CCD Power supply for H1, H2 Note NOTE: Fixed mode shutter speed control Shutter Speed System S2 0 0 0 0 NTSC 1 1 1 1 0 0 0 0 PAL 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Expected 1/60 1/250 1/500 1/1000 1/2000 1/5000 1/10000 Flickerless 1/50 1/250 1/500 1/1000 1/2000 1/5000 1/10000 Flickerless Real 1/60 1/251 1/513 1/1006 1/1936 1/5034 1/10489 Flickerless 1/50 1/249 1/510 1/999 1/1923 1/5000 1/10416 Flickerless NOTE: White Balance Mode WB1 0 0 1 1 WB0 0 1 0 1 White Balance Mode Normal (auto) Cool color temp. One-shot W/B mode Warm color temp. 6 S5C7320X01 DATA SHEET BLOCK DIAGRAM C C D 8 C CS DC 9E T S T 1 T SX TC 0K YY OO 76 YY OO 54 V SYY SOO 432 V YYD OOD 103 CC OO 76 V CCS OOS 543 CC OO 32 CC OO 10 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 VDD5 SECK SECSN SED ADCK V4 SG2 V3 VSS5 SG1 V1 V2 SUB VSS6 H1 H2 VDD6 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 128 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 128 34 33 32 31 30 29 28 27 26 WB1 WB0 WBRNG SS2 SS1 SS0 FSHTR VDDA2 VSSA2 AC VREF IREF VBB COMP AY VSSA1 VDDA1 EHD EVD RSTN SMO SMI SMCK SMCSN BLC DCLP/DEFECT DET & COMP FCM Chroma Processor ENCODER 1HDL Luminance Processor DAC (Luminance) AE/AWB DETECT EVR IF (SIO) 1HDL DAC (Chroma) MICOM I/F (SIO) TG/SSG EEPROM I/F (SIO) 123 V S S 1 PX C1 1 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SV HD DD 1 C L P 1 2 C L P 3 4 PVH BDD L K FVL LSS DSF 2E CP SA YL N C H I G H C C I R V D D 2 S R D A O S R D A I S R C K M I C O M XRS 2GH P Figure 2. Block Diagram 7 DATA SHEET S5C7320X01 CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Item DC supply voltage (digital) DC supply voltage (analog) DC input voltage Storage temperature Latch-up current Symbol VDD VDDA VIN TSTG ILU Rating -0.3 -- 3.8 -0.3 -- 3.8 -0.3 -- V + 0.3 DD -40 -- 125 100 Unit V V V C mA Remark DAC power - OPERATION TEMPERATURE (0 C -- +70 C) ELECTRO-STATIC CHARACTERISTICS Item Human body model (HBM) Machine model (MM) Electrostatic Standard Pin No All Design Goal 2000V 300V V V Unit Remark ELECTRICAL CHARACTERISTICS (AC) VSS = 0V, VDD = 3.3V 10%, Ta = 0 -- 70C Table 2. Electrical Characteristics (AC) Item Input data setup time Input data hold time Signal CCD9 - CCD 0 CCD9 - CCD 0 Symbol Min Tsu Thd 5 5 Design Goal Typ Max 50 ns ns VDD = 3.3V 10% Ta = 0 - 70 C VDD = 3.3V 10% Ta = 0 - 70 C Unit Remark X1 Thd CCD9 ~ 0, Tsu 8 S5C7320X01 DATA SHEET Appendix: External Synchronization Configuration Example of Internal Reset Mode (NTSC) EVD EHD Sync. Separate TG/SSG VD Vsync Hsync HD LPF /VCO X-Tal 1 XCK R PC1 V 1/2 1/606 1/262.5 Figure 3. Example of Internal Reset Mode (NTSC) Example of Line Lock Mode (NTSC) EVD EHD Sync. Separate TG/SSG VD Vsync Hsync HD LPF /VCO X-Tal 1 XCK R PC1 V 1/2 1/606 1/262.5 Encoder Clock Figure 4. Example of Line Lock Mode (NTSC) 9 DATA SHEET S5C7320X01 Example of H Reset, V Reset Mode (NTSC) EVD EHD Sync. Separate TG/SSG VD Vsync Hsync HD LPF /VCO X-Tal 1 XCK R PC1 V 1/2 1/606 1/262.5 Figure 5. Example of H Reset, V Reset Mode (NTSC) Example of H PLL, V Reset Mode (NTSC) EVD EHD Sync. Separate TG/SSG VD Vsync Hsync HD LPF /VCO X-Tal 1 XCK R PC1 V 1/2 1/606 1/262.5 Figure 6. Example of H PLL, V Reset Mode (NTSC) 10 S5C7320X01 DATA SHEET Example of Csync Reset (H PLL, V Reset) Mode (NTSC) EVD EHD Sync. Separate TG/SSG VD Vsync Hsync HD LPF /VCO X-Tal 1 XCK R PC1 V 1/2 1/606 1/262.5 Figure 7. Example of Csync Reset (H PLL, V Reset) Mode (NTSC) PLL Application Circuit S5C7320X01 From External EHD EVD X1 X2 PC1 Figure 8. PLL Application Circuit 11 DATA SHEET S5C7320X01 APPLICATION CIRCUIT DIAGRAM EXT. DC EVI E CD C C S 10BIT D AG C AD C VD CCD8 C CCD7 C D CCD6 9 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 VDD5 SECK SECSN SED ADCK V4 SG 2 V3 VSS5 SG 1 V1 V2 SUB VSS6 H1 H2 P VDD6 C VSS11 0 S T T X Y Y Y Y V Y Y Y Y V C C C C V C C C CO C S S C OO O O S OO O O DO O OO S OO OW B1 E TT K76 5 4 S32 1 0 D7 6 54 S32 1 W B0 10 4 3 3 W BRNG SS2 SS1 SS0 FSHTR VDDA2 VSSA2 AC VREF I REF VBB CO P M AY VSSA1 VDDA1 EHD EVD RSTN SM O SMI CC C SS SM CK VLS HCVRRS VLLP SM SSDPPB F S S Y P I C D D D R CSN X X R H H D 1 3 L V H L S F N A G I D A A C BLC 1 2 G P D 1 2 4 K D D D 2 E C L H R 2 O I K MI CO M SH TTER U & W TE BLANCE HI M D SETTING OE 38.5U C 1. 0V 564U A S5C7320X01 38.5U A Y SYSTEM MI C M O EEPRO M MD OE SETTI N G Figure 9. Application Circuit Diagram 12 S5C7320X01 DATA SHEET PACKAGE DIMENSIONS UA : (R) 16.00 BSC 0~7AE 14.00 BSC 0.09 ~ 0.20 14 00 BSC #1 16 00 BSC KS7320 0 603/40 15 #100 0.17~0.27 (1.00) 0.50 BSC U|0.08MAX 0.05 ~ 0.15 1.003/40.05 1.20 MAX |0.08 MAX Figure 10. Package Dimensions 13 |
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